1. Field of the Disclosure
The present invention relates to a semiconductor device and a method for manufacturing the same. More particularly, the present invention relates to a lateral double diffused metal oxide semiconductor (LDMOS) device and a method for manufacturing the same.
2. Discussion of the Related Art
As follows, a conventional lateral double diffused metal oxide semiconductor (LDMOS) transistor will be described in reference to corresponding drawings.
FIG. 1 is an overhead view illustrating a conventional LDMOS transistor.
In reference to FIG. 1, at least one metal line 20 and a contact 22 are formed and a dielectric layer 10 is formed between the metal lines 20.
FIG. 2 is a cross-sectional view illustrating the LDMOS transistor cut away along line A-A′ shown in FIG. 1. FIG. 3 is a cross-sectional view illustrating the LDMOS transistor of FIG. 1 cut away along line B-B′ shown in FIG. 1.
In reference to FIGS. 1 and 2, an n-type well 38 is formed in an n-type substrate 30 having an active region defined by an isolation layer 36. A p-type body region 60 and n-type extended drain regions 32 and 40 are spaced apart by a predetermined distance within the n-type well 38. An n+-type source region 62 is formed in a predetermined top surface area of the substrate, adjacent to the p-type body region 60. A channel region of the LDMOS transistor lies below the gate dielectric layer 72 and gate conductivity layer 70, formed thereover. Two n+-type drain regions 34 and 42 are formed in substrate 30, adjacent to the n-type extended drain regions 32 and 40, respectively. A gate spacer layer 76 is formed on a side wall of the gate conductivity layer 70. The space layer 76 may be formed of two dielectric layers 72 and 74. Although not shown in the drawings specifically, a first ion implantation is performed before forming the gate spacer layer 76 to form the p type region 60. After forming the gate spacer layer 76, second ion implantation is performed to form n+ type source and drain regions 42, 62, and 34. Silicide layers 50 are then formed over the drain regions 34 and 42, the source region 62, and the gate conductivity layer 70. As a result, a completed LDMOS transistor structure is formed, as shown in FIG. 2.
Dielectric layers 80, 82, 84, 90, 92, 94, 96, 100 and 102 are formed over the LDMOS transistor structure described above. Contact plugs 22 are formed within the dielectric layers. As shown in FIG. 2, each of the contact plugs is in contact with a corresponding metal line, e.g., metal lines 91, 93 and 98. Contact holes (not shown) are formed in the dielectric layers prior to depositing the contact plugs 22. Also, a contact barrier layer 24 is formed in the contact holes prior to forming the contact plugs 22, and is in contact with the dielectric layers and the silicide layers 50. As shown in FIGS. 2-3, the contact barrier layer 24 is on an outer surface of the contact plugs 22, and is thus interposed between the contact plugs 22 and the dielectric layers and silicide layers 50.
The above LDMOS transistor includes as many contact plugs as possible having minimum design rules to enable the delivery of operation voltages and currents in a substantially short time period. The large number of the contact plugs is advantageous to have a transistor that can deliver many currents simultaneously in a highly limited space. As transistor devices become increasingly miniaturized, the space in which contact plugs are formed is progressively limited. The present invention is directed toward providing an improved contact plug structure that enables miniaturization of ultra large scale integration (ULSI) era transistors.